The datasheet is not very clear about the Clock Division Reg for SPI Master mode,
Suppose i am using fSys= 24MHz
SPI0_CK_SE = 0x10 -> should give a SCK of 1.5MHz correct?
SPI0_CK_SE = 0x20 then 750kHz
...
What will happen for SPI0_CK_SE=0; Do I get a SCK of 24MHz/ 256?
I am asking because i have no hardware ready right now to check the divider.
Another Questtion:
Do i need to activate PUSH/PULL config for the outputs or is it sufficient just to set the OE bits
bS0_MOSI_OE,bS0_SCK_OE,bS0_MISO_OE